Berkeley Out-of-Order RISC-V Processor (Boom) (2020)

35 pointsposted 16 hours ago
by Bogdanp
(docs.boom-core.org)

19 Comments

camel-cdr

13 hours ago

RISC-V is still at the point where open-source implementations (in rtl) are faster than purchasable proprietary ones (in silicon).

XiangShan is currently the fastest open-source CPU implementation: https://github.com/OpenXiangShan/XiangShan

uarch slides: https://tutorial.xiangshan.cc/hpca25/slides/20250302-HPCA25-...

uarch slides with WIP features: https://tutorial.xiangshan.cc/micro25/slides/Microarchitectu...

kragen

11 hours ago

Do you expect that to change at some point?

camel-cdr

11 hours ago

Yes, but keep in mind that I'm purposfully comparing development RTL on the open-source side with finished silicon product on the proprietary side.

Many companies have production ready/fully verified IP that are much faster than XiangShan, but they haven't taped out and productized it yet.

E.g. Tenstorrent Ascalon IP is available and at 21 SPECint2006/GHz. They want to release a lower clocked devboard on TSMC 12nm in 2026 Q2.

XiangShan is currently at 15 SPECint2006/GHz, but are targeting 22 SPECint2006/GHz in the next iteration, that is currently in the works. Well have to see who gets there first.

The inherent gap between RTL design and final product may be large enough that open-source RTL can keep up in terms of IPC, if XiangShan continues their momentum. But I think open-source trailing 1-3 years is a more realistic long term outcome.

rwmj

11 hours ago

I've just seen a demo of a very high performance RISC-V chip (actual silicon) that'll blow the doors off other implementations. Under NDA of course.

Actually available for pre-order, take a look at the UltraRISC DP-1000 (unrelated to the chip above).

kragen

11 hours ago

Excellent! But probably open-source implementations will also continue to improve.

0x000xca0xfe

11 hours ago

Can you share any details? Like potential year of release?

rwmj

11 hours ago

That's actually the most NDA thing, since companies don't want to be held to a release date. However the fact they have fully functional engineering samples running in their offices now is very encouraging.

user

11 hours ago

[deleted]

huyage

14 hours ago

If I want to do systems research that needs a simple and synthesizable RISC-V design, what are some good options? BOOM seems to be pretty complicated and I don't really need the out-of-order execution.

I also want to be able to run it on a cheap FPGA, something like Artix A7.

panick21

12 hours ago

This is what the OpenHW Foundaiton is for. Providing well verified cores for people who just need a core. They are based on the original Pulp Cores from the ETH Zürich and Unviersity of Bolongia. See:

https://openhwfoundation.org/

Or because its part of OpenTitan, Ibex sees a lot of development: https://github.com/lowRISC/ibex

kragen

11 hours ago

Claire Wolf's PicoRV32 seems to get a lot of "simple and synthesizable RISC-V design to run on a cheap FPGA" use, although that's more typically for much cheaper FPGA's than an Artix A7, like an iCE40. SeRV is even cheaper and simpler but much slower. Graeme Smecher’s RVC-first "Minimax" is almost as simple as SeRV but not nearly as slow.

I haven't tried any of them, though, so take this with a Himalayan salt lamp.

jhallenworld

9 hours ago

I've been getting tremendous use out of PicoRV32- it works, it's tiny, and for many use cases ("management plane") you just don't need much speed. I work around its slowness by providing things like relatively large communication buffers in the FPGA. I use it in "execute in place" mode from external SPI-flash (the FPGA's config flash), but with an instruction cache. It can do floating point via emulation which is handy for printf.

I've been meaning to update my toolbox to at least a pipelined processor of some sort (to up the IPC rate to at least 1), but so far just had no strong need. For applications that really need CPU power, I use SoC FPGAs like Zynq.