Releasing Open Source RISC-V Configurable In-Order/OoO Multi-Core+AI Processor

2 pointsposted 10 hours ago
by etcimon

1 Comments

etcimon

10 hours ago

https://imgur.com/a/dnT0pOJ

Releasing GSys LibreCore today, includes a bios, sv-timing adjustments (3ghz+) configurable to multi-core, multi-issue with QEmu and heavily tested for SMT2.

The AI Processor has shown promising results with 40x speed improvements on VA-Turbo

Agentic-friendly RISC-V development with state-of-the-art features

Read more on Github https://github.com/etcimon/GSys-LibreCore