mikeayles
4 hours ago
The space is definitely heating up.
Flux.ai being the incumbent Silixon based out of the UK have been showing demos Quilter and DeepPCB for layout The recent OpenAI demo...
I went the other way and pre-designed sub circuits with a set of rules that allows simple merge assembly, unfortunately I didn't have the time or budget to continue with it, but I took the constrained approach as with hardware, things can't be 99%.
The one thing I will say, is that my experience of hardware engineers is very gatekeepy.
Any questions about the use of AI for any form of automation on forums/Reddit get shot down instantly and the OP's told 'skill issue' more or less. In my opinion, just as with software, most work is simple and should be automated, there will always be a need for the real engineering when it comes to high specification work, high volume optimisation and hardware debug (although Claude code is pretty handy at driving a Jlink)
Aurornis
3 hours ago
> The one thing I will say, is that my experience of hardware engineers is very gatekeepy.
Stay away from Reddit and forums if you want to see where the open minded people are looking. There are a lot of communities where EEs are experimenting with newer technologies and sharing their results, with realistic appraisals of what can be done.
You also need to understand the history of autorouting technology for PCBs. Autorouters with auto layout have been around in many forms for years. Their output never compares to a skilled EE doing it manually. The gap between autorouter output and skilled operator output is even bigger than the gap between a good developer and average AI codegen slop.
I’m interested in this space, but even the Fable/Astra or dedicated tools like Quilter, Flux, and others have a very, very long way to go for boards more complex than simple hobby boards.
I do think this is going to be good for hobby people doing simple PCBs though
stonogo
2 hours ago
> Stay away from Reddit and forums if you want to see where the open minded people are looking. There are a lot of communities where EEs are experimenting with newer technologies and sharing their results, with realistic appraisals of what can be done.
Where are these communities?
Joel_Mckay
3 hours ago
NP-hard problems are still NP-hard even with magical LLM pixie sprinkles. =3
Aurornis
2 hours ago
If the magic LLM pixie sprinkles can brute force their way to a solution using viable heuristics and their training data, I will use them.
Joel_Mckay
an hour ago
NP-Hard is NP-hard... "heuristics" in this case is just a euphemism for a fantasy cost-function to scam shareholders.
It is a named problem, and can't be misappropriated like the $9Tn worth of FOSS code "AI" scraped and compacted for isomorphic plagiarism tokens. =3
officialchicken
2 hours ago
Magical LLM pixie sprinkles ... is that where magic smoke comes from?
Joel_Mckay
an hour ago
Magic smoke is important, as it indicates a design parameter was exceeded.
I often recommend folks get a mini thermal camera for their phone... as inspecting for issues in electrical, hydraulic, or mechanical systems gets a fair bit easier/safer. =3
monocasa
2 hours ago
They're also NP-hard for the humans doing the majority of the work currently, meaning that good enough heuristics dominate as it is.
Joel_Mckay
2 hours ago
Every trace on a PCB is a traveling salesman problem with ballooning complexity.
https://en.wikipedia.org/wiki/Travelling_salesman_problem
While physics informed models do exist, they are still going to burn a lot of compute to generate failure modes people didn't know were possible. =3
monocasa
14 minutes ago
Well, no, it's not.
If anything, it's closer to the bin packing problem. The cost function isn't expressed in terms of lowest cost between nodes, but instead fitting all of the traces with the lowest board layer count while still meeting stuff like EMI crosstalk guidelines. Then there'll be some traces that are very constrained (think DRAM or SERDES links) that have to be length matched, but those are pretty much invariably point to point links that already are heavily automated.
Traces being, say 20% longer than they need to be for an optimal solution doesn't really change the performance of the board in the vast majority of cases since they'll be some of the lowest resistance components of the netlist anyway, as well as the fact that the PCB is normally oversized for the number of traces needed as it fulfills structural/mechanical needs as well as the netlist needs.
And on top of that, because the optimal solution probably is NP-hard, once again, the industry doesn't look for optimal, only good enough. If layout techs in Altium were regularly solving NP-hard problems, computer science would be a different place. The only goal I see is to meet that bar without hiring layout techs.
Joel_Mckay
3 minutes ago
>Traces being, say 20% longer than they need to be doesn't really change the performance of the board
Impedance matching requires you know what you are doing, and Altium will only take you so far. For the price, Altium/Protel has always been a poor deal for what you get software wise.
Even free Qspice (a more modern Analog Devices LTSpice) is a far better option:
https://www.qorvo.com/design-hub/calculators-simulation/qspi...
>the industry doesn't look for optimal, only good enough
Indeed, that is why your iPhone still weighs 3.7 kg. =3
HeyLaughingBoy
an hour ago
My experience with hardware engineers, at least IRL, is very different. They love to talk about their work. However, I used to be an EE so that probably helps.
As for Reddit, there's a lot of "bury head in sand and problem will go away" behavior when it comes to AI. People are understandably worried about their jobs, but they're certainly not doing themselves any favors by downplaying AI or looking for "tech niches where AI isn't yet."
Copperhead is very interesting. I do some embedded systems consulting on the side, but I've never enjoyed PCB layout very much. I briefly investigated using AI for it the last time I had to do a board, but it wasn't very helpful.