__rej__
12 hours ago
FYI this how chip looks right now in the 5 mm^2 configuration.
https://github.com/rejunity/z80-open-silicon/blob/main/docs/...
The colourful lines in the middle are the metal wires (layers 2,3 & 4) displaying the interconnect inside the chip and connections to the I/O pads which in turn will be wirebonded to the external pins.