Fifty Celsius is an insane drop.

It sounds like the most important part of the article (and another cool quote) is this:

>Until recently we knew how to grow it only at circuit-slagging temperatures in excess of 1,000 °C.

So basically, the big breakthrough was low-temp growth of a diamond lattice. Very cool they can do it at such a low temperature. It must be a crazy low temp - probably under 100C?

The editors at IEEE Spectrum are very good at improving articles. They also thoroughly fact-check articles. (Source: I wrote a couple of articles for IEEE Spectrum.)

Spectrum is typically pretty good, but this article definitely stands out as very well written. I'm guessing that's because it's written by an actual contributor to the research. Nothing beats when those guys can actually unpack an idea simply.

Putting on my frowny-faced principal engineer hat: we need someone to do the calculation of cost of manufacturing vs the amount of money saved by increasing energy efficiency.

As the article you link says:

> The high p-n junction built-in voltage (4.9V, compared to 2.8V in SiC) and short carrier lifetimes limit the advantages of bipolar diamond devices to only ultra-high voltages (> 6kV) and low switching frequencies.

Nobody is thinking about using diamond for the silicon CMOS logic in a computer, though they may replace the gallium arsenide we use for motor control some day.

Diamond is a wide-bandgap semiconductor; if it can be made to work, it would couplete with GaN and SiC, not silicon.

Cue Neal Stephenson’s “the Diamond Age”

Even according to the article: "2,200 to 2,400 watts per meter per kelvin - roughly six times as conductive as copper.". It's way higher than copper in fact. Copper is ~400 W/(m·K)

May our children live to use high-end diamond cookware

"Diamond substrate breakthrough enables faster chips."

So? You're always going to hit some constraint. Such is the nature of physical reality after all. Advances in the field are all about pushing past the current blockers to the next ones.

These are gigantic and interesting questions packed into some pretty tiny boxes :) I will try to capture some of the issues involved.

Caveat: For older processes, built on a larger scale (>1 micron), these kinds of details may not matter, in which you are right to question this point. But if you want to implement on cutting edge manufacturing processes, these details absolutely do matter.

To put this in perspective, in cutting edge process nodes, I've seen senior engineers argue bitterly over ~1 nm in a certain critical dimension. That's (roughly) about 5 atoms across, depending on how much you trust the accuracy of the metrology.

So, if ANY layer isn't "flat" (or otherwise to spec within tolerance), the next layer in the semiconductor patterning stack will tend to translate that bumpiness upward, or cause a deformity in adjacent structure. This is (almost) always bad. These defects cause voids, bad electrical/thermal contacts and characteristics, misshapen/displaced structures, etc, etc

Crystallization in thin-film (especially conformal/gap-filling films) is a tough job which many poor PhD students have slaved over. Poly crystalline material is arguably harder to control in some key ways vs mono crystalline, since you don't have direct control the specific crystal grain orientation and growth direction. That is, some grain orientations will grow quickly, and others growing slowly. You can imagine the challenge then of getting the layer to terminate growth without ending up too jagged on the ~nm scale. After that you also get into the fun world of crystal defects, grain size, and deciding if you need to do some more post-processing (do I risk planarizing?)

Hopefully I have captured some of the pieces involved in an understandable way.

Edit: clarity

All semiconductor manufacturing techniques are based upon precisely flat layers of material that can be stacked and/or drilled into to produce a useful design. All vertical irregularities propogate to the layers above and can cause thinner layers when an upper layer is milled flat

Presumably it's to ensure good contact with the next thermal management layer (heat spreader, heat-sink, etc.)

It’s difficult to cmp diamond is the issue I’d assume

I think cooling in a chip vs cooling in space are two orthogonal problems. In a chip, the problem is getting the heat to the heatsink where it can be efficiently dissipated into the much larger heatsink of the surrounding environment. In space, the problem is that the only way to dissipate heat is thermal radiation because you're in a vacuum.

DLC (diamond-like carbon) generally lacks long-range crystalline order. It's thermal conductivity is quite low.

I joked about it last year[0], but before going for isotopically pure diamond they first have to make them single-crystal, the grain boundaries are worse than isotopic impurities.

[0] https://news.ycombinator.com/item?id=39742447

This is polycrystalline diamond, which probably scatters phonons anyway, so it seems naively like using a single isotope wouldn't help much. But that's definitely an interesting fact and I think you're right that it probably wouldn't add much expense when the amount of material is so small.

NAND flash memory chips these days are manufactured with low hundreds of layers of memory cells on each die, so they're probably some of the thickest individual dies. They are commonly packaged with up to 16 dies per package, usually in one or two stacks. Those packages are usually under 3mm thick.

The packaging usually has the stacked dies offset in a staircase pattern so that the contacts at the edge are exposed for every die. The alternative is through-silicon vias (TSVs), which theoretically would allow stacking until you have a mass of chips that is roughly a cube, but achieving that without having a defective connection somewhere in the stack is approximately impossible.

When you use Through-Silicon Vias (TSVs) to connect the layers together, you would start to end up with scaling limits, similar to the problems of elevators in skyscrapers: the more layers you have, the higher the density of TSVs would (presumably) be required.

This is probably not an issue for thermal TSVs, because of the heat spreader layer between each silicon layer, but it would become an issue for power TSVs, as each layer would (presumably) require an independent supply of power.

Oh man, the integrated problems this will cause for the manufacturing engineers will be of nightmare level. You wont really get to properly test how well you made the heat pipe network until end of line! Hopefully they will be able to drum up some inline metrology to test the heat pipes before then...

This on top of all the through-silicon-vias and backside power delivery would make even the crustiest of engineers weep...