ulfw
5 hours ago
Very interesting to see. Efficiency (E) cores use only 7% of the energy that Performance (P) cores do performing the same task and take about 4x as long to do it.
So about 13.5x (23 J when run on P cores, and less than 1.7 J when run on E cores) the power to do about 4x the performance
user
5 hours ago
jbverschoor
4 hours ago
So BeOS has a place in this universe
cubefox
5 hours ago
This may come largely from clock speed needing disproportionately more/less energy the higher/lower it goes.
This answer (based on an old source) even says power consumption increases with the cube of the clock speed: https://physics.stackexchange.com/posts/61937/revisions
Though this would mean a 4x in clock speed would consume 4^3=64 times as much energy, which is more extreme than what is observed here in the Apple chip. So either the clock speed/power relation is different now or the P cores do not actually have a 4x scaling in clock speed. Cache size etc may also play a role in performance.
huijzer
5 hours ago
Isn't that called Dennard scaling [1]?
cubefox
4 hours ago
No, the "cube law" is related to varying clock speed rather than to varying transistor size.
formerly_proven
3 hours ago
Per the article, the clock speed difference is much smaller than the ~4x performance difference (4.5 GHz vs 2.6 GHz, i.e. 1.7x). So more than half of the performance advantage of the P cores has to come out of the uarch difference (wider structures etc.). Meanwhile there will be other factors besides clock frequency, e.g. the P cores might use a different cell library than the E cores.
cubefox
2 hours ago
Makes sense. This would suggest the difference in power draw may not mainly come from the clock frequency, since (1.7x)^3=5x, which is significantly less than the 13.5x in power draw.
raverbashing
5 hours ago
I wonder what changes? In-order vs OOO? Less int/fp units? Are they fully instruction set compatible?
nsbk
5 hours ago
From the article about the instruction set:
> This is believed to be identical to ARMv9.2-A without Scalable Vector Extension (SVE) supported by M4 P cores, enabling the same threads to be run on either core type.
It also explicitly mentions half of the processing units per core and lower clock speeds.
bayindirh
5 hours ago
No they are not. "Efficiency" cores are generally tailored to do simple stuff well. Less floating point, more integers. Like file parsing, serving web pages, responding to network events, whatnot.
When you need heavy computation (encoding, scientific, etc.) P cores are your only choices.
As a result, server ecosystem will be fragmented a bit. For HPC and calculation stuff, P-Core heavy processors will be sold. For cloud and CRUD systems, E-Cores will dominate.
JohnBooty
an hour ago
From the article:
"[The E cores'] instruction set is the same as M4 P cores, ARMv9.2-A without its Scalable Vector Extension (SVE)"
formerly_proven
3 hours ago
Curiously we had this argument before, roughly two decades ago.
bayindirh
2 hours ago
Doesn't this happen in cycles? A specialized hardware appears, then it gets integrated into processor to make way for an even more specialized variant of the thing, rinse and repeat.
This external thing doesn't have to be "more powerful" per se. So, E cores are lower power helpers which are implemented back into the CPU in a slightly altered form.
Who or which prevents them from being dedicated to processing a network stream or just handling network thread of a service, making them "efficient accelerators" in a sense?
saagarjha
5 hours ago
No, yes, yes
whereismyacc
5 hours ago
Isn't basically every modern cpu core OOO?