The world would be much nicer if we still had new Alpha CPUs. It was intended to be a CPU architecture that lasts 25 years and Digital intended the architecture to support a 1000x increase in performance during that time.

Now we have RISC-V reinventing the wheel. Not the worst outcome, but we could have had it so much better...

The Itanium architecture is a weird weird architecture. It's not weird in the sense of Alpha's weirdness (e.g., the super weak memory model), which can be fairly easily compensated for, but it's weird in several ways that make me just stare at the manual and go "how are you supposed to write a compiler for this?" It's something that requires a sufficiently smart compiler to get good performance, while at the same time so designed as to make writing that sufficiently smart compiler effectively compiled.

It wouldn't surprise me if Itanium actually had pretty compelling SPECint numbers. But a lot of those compelling numbers would have come from massive overtuning of the compiler to the benchmark specifically. Something that's going to be especially painful for I/O-heavy workloads is that the gargantuan register files make any context switch painfully slow.

> The Apache #’s pretty much give the game away: An Itanium clocked 50% higher was losing to a 2yo Alpha by about 20% on throughput at peak.

This is not just a benchmark of the CPUs, but also of the compilers involved. It is well-known that it was very hard to write a compiler that generates programs that could harness the optimization potential of Itanium's instruction set.

Itanium was primarily developed by Intel, Itanium 2 primarily by the HP team that also was responsible for the competitive PA-RISC chips. (Or so they say). In any case, Itanium 2 still outperformed much later AMD Opterons and Intel Xeons running at twice the clock in numerical workloads. That’s pretty impressive.