Bendable non-silicon RISC-V CPU demoed running while wrapped around a pencil

16 pointsposted 13 hours ago
by Cipher_Forge

7 Comments

tofof

12 hours ago

From the associated paper:

"Flex-RV also integrates a programmable machine learning (ML) hardware accelerator inside the microprocessor and demonstrates new instructions to extend the RISC-V instruction set to run ML workloads. It is implemented, fabricated and demonstrated to operate at 60 kHz consuming less than 6 mW power."

marshray

9 hours ago

I don't want to be dismissive or overly critical of new technology.

But this is a 1960's era microprocessor: resistor-transistor logic running at 60 kHz. Something like the Apollo guidance computer, but at a 17 times slower clock speed.

The CPU is bit-serial: one bit at a time.

It saddens me they felt they needed to bolt-on some 4x8 bit multipliers. It feels like they just wanted to claim "the first flexible microprocessor with embedded ML capabilities".

https://en.wikipedia.org/wiki/Resistor%E2%80%93transistor_lo...

brucehoult

4 hours ago

Sometimes simply being programmable is enough, you don't need all that much speed.

SeRV at 60 kHz is going to do between 1000 and 2000 instructions per second, depending on the instruction mix.

As something to compare that against, an Apple ][ running AppleSoft BASIC runs `FOR I=0 TO N:T=T+I:NEXT I` at 250 loops per second.

On SeRV that loop is going to be something like ...

    loop:
        add  a1,a1,a2
        addi a2,a2,1
        bge  a0,a2,loop
... which will take 96 clock cycles per iteration, or about 600 loops per second at 60 kHz, so that's 2.4x faster than AppleSoft on an Apple ][. Which many people found fast enough to start a revolution.

Yes, AppleSoft is using floating point numbers, which are slower than integers, but Integer BASIC only runs that same code at about 330 loops per second.

Original IBM Model 5050 PC runs the same loop at 415 loops per second in BASIC (380 for BASICA), if that's your reference ecosystem. Not a big difference. Still slower than SeRV at 60 KHz.

brucehoult

24 minutes ago

Oops, sorry, that RISC-V code will be 128 cycles per loop on SeRV not 96, as the branch needs 64 cycles. So about 470 loops per second not 600 on that flexible chip.

Of course this doesn't alter the point about being as fast as the BASIC that early PCs came with, the only thing most end users had to write their own programs on them until things such as Turbo Pascal appeared (November 1983).

jl6

12 hours ago

A key enabler of a nightmare dystopia is not being able to tell whether everyday items are secretly working against you. This tech seems to open up new horizons in the field of untrustworthy objects.

alchemist1e9

12 hours ago

Imagine clothing made of it. I think that would be pretty neat future. Wearing a supercomputer that also keeps you warm!

user

12 hours ago

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